Leakage Power and Area Optimization in Cmos Logic Design in Sub Micron Technology (2025)

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

International Journal of Computer Applications, 2013

IJERT-Comparison of Various Leakage Power Reduction Techniques for CMOS Circuit Design

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design https://www.ijert.org/research/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design-IJERTV2IS100167.pdf Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground.We have compared different approach, named “sleepy keeper,” which reduces leakage current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus two additional transistors – driven by a gate’s already calculated output – to save state during sleep mode. In short, like the sleepy stack approach, sleepy keeper achieves leakage power reduction equivalent to the sleep and other approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered).. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon in a VLSI designer's arsenal

MINIMIZING THE SUB THRESHOLD LEAKAGE FOR HIGH PERFORMANCE CMOS CIRCUITS USING STACKED SLEEP TECHNIQUE

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. For the most recent CMOS feature sizes (e.g., 45nm and 65nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. In the nanometer technology regime, power dissipation and process parameter variations have emerged as major design considerations. These problems continue to grow with leakage power becoming a dominant form of power consumption. Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS).This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques at circuit level and process level are used to efficiently minimize leakage current which lead to minimize the power loss and prolong the battery life in idle mode. This paper presents a technique for minimizing sub threshold leakage current using stacked sleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack, Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model. The proposed technique dissipates lesser static power and lesser delay product compared to the previous technique. An improvement of 1.2X was observed in static power dissipation in comparison with conventional approach, thus maintaining the state of art of the logic in the digital circuit.

Efficient reduction of leakage power in low power VLSI circuits using Sleepy Keeper Approach

2015

62 www.ijeas.org  Abstract— Voltage Scaling in CMOS circuits will reduce the threshold voltage, however there is an increase in the sub threshold leakage current and hence static power dissipation. This increase in leakage power dissipation is a concern in VLSI design even for the most recent CMOS feature sizes. To reduce this power dissipation an approach called sleepy keeper is used for CMOS circuits. This approach uses two additional transistors along with the traditional sleep transistors. These additional transistors help to save a logic state during the sleep mode.

Standby Leakage Power Reduction Techniques in Deep Sub-Micron CMOS VLSI Circuits

Ijca Proceedings on International Conference on Communication Technology, 2013

IJERT-Leakage Power Reduction in CMOS VLSI

International Journal of Engineering Research and Technology (IJERT), 2014

https://www.ijert.org/leakage-power-reduction-in-cmos-vlsi https://www.ijert.org/research/leakage-power-reduction-in-cmos-vlsi-IJERTV3IS051384.pdf With rapid changes in semiconductor technology chip density and frequency have increased, making the power consumption one of the major concern. Thus low power design has become the major challenge for present designers. Report says that 45% or even higher percentage of total power consumption is due to the leakage power of transistors. So reduction of leakage power is a great challenge for current and future technologies.in this paper, we are going to discuss different techniques for reducing the leakage power like dual threshold, transistor stacking, sleepy approach and variable threshold in CMOS VLSI circuit.

Standby Leakage Power Reduction in Digital Circuits

2015

As MOSFET dimensions shrink to the nanometre scale, the leakage power and negative-bias temperature instability (NBTI) become a challenging issue. Leakage power can be decrease by Stack transistor, Sleep transistor and transmission gate base techniques. Sleep transistor technique provided lesser static power dissipation and lesser static power delay product in comparison with the other techniques. It has been shown previously that the stacking of two off transistors has significantly reduced subthreshold leakage compared to a single off transistor. In this work a stack transistor technique using two series connected stack is use to design the digital circuit. But it has a delay penalty. The static and dynamic power of stack is considerably low. But it has a delay penalty and its area requirement is maximum compared with other processes. This can be overcome by using stack transistors of half size. Our goal is to trade off between these limitations and thus propose new methods which ...

AN EFFICIENT METHOD FOR REDUCING LEAKAGE POWER IN VLSI DESIGN

Portable electronic devices are integral components in our daily life. These devices require charging after a certain amount of usage time. Most of the time during discharging cycle, they remain idle or inactive. Even though the devices are not in active use, there is a leakage power consumption with downward scaling of technology. So there is need to reduce leakage power consumption for that we are proposing a method called stacked sleep transistor technique and also going to analyze for different logic circuits by using SAED 90nm technology. This approach is going to analyze over existing methods like Sleep Transistor Technique , Sleepy Stack Technique and Sleepy Keeper Techniques such that we are going to reduce leakage power and power delay product. so that device performance is going to increase.

Minimizing the Sub Threshold Leakage for High Performance Cmos Circuits Using Novel Stacked Sleep Transistor Technique

2012

2This paper presents a technique for minimizing sub threshold leakage current using stacked sleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack, Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model. The proposed technique dissipates lesser static power and lesser delay product compared to the previous technique. An improvement of 1.2X was observed in static power dissipation in comparison with conventional approach, thus maintaining the state of art of the logic in the digital circuit.

Review of Leakage Power Reduction in CMOS Circuits Cite This Article